Rate Change Use Mode without Reference Clock Change

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

If the reference clock frequency does not need to change, the user shall use the rate change port and wait for the CH*_TXRESETDONE or CH*_RXRESETDONE assertion to signal the rate change process completion. The following timing diagram shows the sequence details.

Figure 1. Transceiver Rate Change with No Changes in Reference Clock