Reading Datapath Latency

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The datapath latency through the RX async gearbox FIFO is calculated statistically using RXLATCLK, which is asynchronous to RX_PHYCLK. SAMPLE_PERIOD in CH*_RX_PCS_CFG2 determines the number of RXLATCLK cycles over which averaging takes place. The measured latency value in RXGBOX_FIFO_LATENCY is updated once per sampling period, which is defined in SAMPLE_PERIOD.

For the read side of the RX async gearbox FIFO, there is an additional offset that is determined by the gearbox slip count value for the data alignment. Thus, the CH*_RXGEARBOXSLIP must be performed to achieve sync status prior to reading out the latency value. The latency measurement is not supported in CAUI mode.

These settings are used to read the latency:

  • Enable RX asynchronous gearbox under normal mode.
  • Set CH*_RX_PCS_CFG2[12:10] (SAMPLE_PERIOD):
    • A higher averaging period gives a more accurate latency value.
  • Achieve datapath sync status by CH*_RXGEARBOXSLIP.
    • The value is in units of 1/8 UI.
    • The actual latency is RXGBOX_FIFO_LATENCY plus a fixed value.