TX Buffer Bypass in Single-Lane Auto Mode without Asynchronous Gearbox

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Use these transceiver settings to bypass the TX buffer in single lane mode:

  • CH*_TX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)
  • CH*_TX_PHALIGN_CFG1[2:1] = 2'b00 (CHAIN_MODE)
  • CH*_PIPE_CTRL_CFG7[2:0] = 3'b011 or 3'b101 (TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK

With the transceiver reference clock selected, TXOUTCLK is used as the source of TXUSRCLK. You must ensure that TXOUTCLK and the selected transceiver reference clock are operating at the desired frequency. When the TX buffer is bypassed, the TX phase alignment procedure must be performed after these conditions:

  • Resetting or powering up the transceiver TX
  • Resetting or powering up the RPLL and/or LCPLL
  • Change of the transceiver reference clock source or frequency
  • Change of the TX line rate

The following figure shows the required steps to perform the auto TX phase alignment and use the TX delay alignment to adjust TXUSRCLK to compensate for temperature and voltage variations.

Figure 1. TX Buffer Bypass—Single-Lane Auto Mode
  1. The sequence of events in the figure is not drawn to scale.
  2. After conditions such as a transmitter reset or TX rate change, TX phase alignment must be performed to align PHYCLK and TXUSRCLK. The TX phase and delay alignments are initiated by asserting CH*_TXPHDLYRESET.
  3. TX phase alignment is done when the rising edge of CH*_TXSYNCDONE is detected. This signal should remain asserted until another alignment procedure is initiated.
  4. An assertion/deassertion of GTTXRESET is required if CH*_TXSYNCDONE does not follow the sequence shown in the figure.
  5. TX delay alignment continues to adjust TXUSRCLK to compensate for temperature and voltage variations.