Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX clock data recovery (CDR) circuit for each receiver channel in the GTYE5_QUAD or GTYP_QUAD extracts the recovered clock and data from an incoming data stream. The following figure illustrates the architecture of the CDR block. Clock paths are shown with dotted lines for clarity.

Figure 1. CDR Detail

The GTY and GTYP transceiver employs a phase rotator CDR architecture. Incoming data first goes through receiver equalization stages. The equalized data is captured by an edge and a data sampler. The data captured by the data sampler is fed to the CDR state machine and the downstream transceiver blocks.

The CDR state machine uses the data from both the edge and data samplers to determine the phase of the incoming data stream and to control the phase interpolators (PIs). The phase of the edge sampler is locked to the transition region of the data stream, while the phase of the data sampler is positioned in the middle of the data eye.

Figure 2. CDR Sampler Positions

The RPLL or LCPLL provides a base clock to the phase interpolator. The phase interpolator in turn produces fine, evenly spaced sampling phases to allow the CDR state machine to have fine phase control. The CDR state machine can track incoming data streams that can have a frequency offset from the local PLL reference clock.