TX PMA and TX PCS can be reset individually. Component reset is enabled by setting the appropriate TXPMARESETMASK and TXPCSRESETMASK bits along with TXRESETMODE and then toggling GTTXRESET.
Driving GTTXRESET from High to Low starts the component reset process. All TXPMARESETMASK and TXPCSRESETMASK bits along with TXRESETMODE must be held constant during the reset process.
When TXRESETMODE is set to sequential mode, the internal resets are toggled in sequence depending on TXPMARESTMASK and TXPCSRESETMASK selection. When TXRESETMODE is set to single mode, the internal resets are toggled simultaneously depending on TXPMARESETMASK and TXPCSRESTMASK selection. TXRESETDONE does not assert in single mode.
In sequential mode, if the TX PCS is to be reset, TXUSERRDY must assert to High prior to the internal PCS reset signal being released allowing TX reset to be completed.
The following table lists the recommended resets for common situations.
| Situation | Components to be Reset | Recommended TX Reset Setting | ||
|---|---|---|---|---|
| TXRESETMODE | TXPMARESETMASK | TXPCSRESETMASK | ||
| After power up and configuration | RPLL, LCPLL, Entire TX |
2'b00
|
3'b111
|
1'b1
|
| After turning on a reference clock to the LC/RPLL being used | RPLL, LCPLL, Entire TX |
2'b00
|
3'b111
|
1'b1
|
| After changing the reference clock to the LC/RPLL being used | RPLL, LCPLL, Entire TX |
2'b00
|
3'b111
|
1'b1
|
| After assertion/deassertion of LCPLLPD or RPLLPD for the PLL being used | RPLL, LCPLL, Entire TX |
2'b00
|
3'b111
|
1'b1
|
| After assertion/deassertion of TXPD[1:0] | Entire TX |
2'b00
|
3'b111
|
1'b1
|
| TX rate change | TX PMA and TX PCS |
2'b00
|
3'b110
|
1'b1
|
| TX parallel clock source reset | TX PCS |
2'b00/2'b11
|
3'b000
|
1'b1
|