Some high-speed data rate protocols use 64B/66B encoding to reduce the overhead of 8B/10B encoding while retaining the benefits of an encoding scheme. The TX asynchronous gearbox provides support for 64B/66B header and payload combining. 64B/67B is not supported by the TX asynchronous gearbox.
The TX asynchronous gearbox supports 4-byte, 8-byte, and 16-byte TX data interfaces to interconnect logic and requires the use of the 4-byte or 8-byte internal datapath. Scrambling of the data is done in the interconnect logic. The following table shows the valid data width combinations for the asynchronous gearbox.
Internal Datapath Width | Interface Width | PHYCLK (MHz) | TXUSRCLK (MHz) |
---|---|---|---|
32 | 32 | TX Line Rate/32 | TX Line Rate/33 |
32 | 64 | TX Line Rate/32 | TX Line Rate/66 |
64 | 64 | TX Line Rate/64 | TX Line Rate/66 |
64 | 128 | TX Line Rate/64 | TX Line Rate/132 |
While the TX synchronous gearbox requires you to pause transmission of your data during various sequence counter values, the TX asynchronous gearbox allows data to be continuously applied every TXUSRCLK cycle. TX buffer bypass is required when using the TX asynchronous gearbox. The following figure shows the location of the TX asynchronous gearbox. When a 4-byte internal datapath is selected (TX_INT_DATA_WIDTH = 1), 32 bits of data are always output by the TX asynchronous gearbox on every TXPHYCLK cycle. Alternating 34 bits (2-bit header and 32-bit payload) and 32 bits (32 bits payload) of data enter the TX asynchronous gearbox every TXUSRCLK cycle. For an 8-byte internal datapath, 64 bits of data are always output by the TX asynchronous gearbox on every TXPHYCLK cycle. 66 bits (2-bit header and 64-bit payload) of data enter the TX asynchronous gearbox every TXUSRCLK cycle.
When in normal mode, the datapath latency through the TX asynchronous
gearbox is measured internally, and the reported latency can be accessed by reading
a read-only register via APB3. The TX asynchronous gearbox is used in conjunction
with the TX programmable dividers. TXOUTCLKCTL must be set to 3'b101
and an appropriate divide value must be selected
to create the required clock frequency for TXUSRCLK.