Transceiver and Tool Overview

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID: AM002
Release Date: 2023-10-26
Revision: 1.3 English

Transceiver and Tool Overview
Introduction to Versal Adaptive SoCs
Navigating Content by Design Process
Features
Key Differences from Previous FPGA Generations
Versal Adaptive SoC Transceivers Wizard
Versal Adaptive SoC Transceivers Bridge IP
Versal Adaptive SoC Ports and Attributes
Simulation
Ports and Attributes
Implementation
Shared Features
Reference Clock Input/Output Structure
Input Mode
Ports and Attributes
Output Mode
OBUFDS_GTE5
Ports and Attributes
OBUFDS_GTE5_ADV
Ports and Attributes
Reference Clock Selection and Distribution
Intelligent Pin Selection
Ports and Attributes
Ring PLL
Ports and Attributes
LC-Tank PLL
Ports and Attributes
Reset and Initialization
Resetting Multiple Lanes and Quads
Reset Modes
RPLL Reset
LCPLL Reset
TX Initialization and Reset
Transceiver TX Reset in Response to Completion of Configuration
Transceiver TX Reset in Response to GTTXRESET Pulse in Full Sequential Reset
Transceiver TX Component Reset
After Power-up and Configuration
After Turning on a Reference Clock to the LCPLL/RPLL Being Used
After Changing the Reference Clock to the LCPLL/RPLL Being Used
After Assertion/Deassertion of LC/RPLLPD for the PLL Being Used
After Assertion/Deassertion of TXPD[1:0]
TX Rate Change
TX Parallel Clock Source Reset
RX Initialization and Reset
Transceiver RX Reset in Response to Completion of Configuration
Transceiver RX Reset in Response to GTRXRESET Pulse in Full Sequential Mode
Transceiver RX Component Reset
After Power-up and Configuration
After Turning on a Reference Clock to the LCPLL/RPLL Being Used
After Changing the Reference Clock to the LCPLL/RPLL Being Used
After Assertion/Deassertion of LC/RPLLPD for the PLL Being Used
After Assertion/Deassertion of RXPD[1:0]
RX Rate Change
RX Parallel Clock Source Reset
After Remote Power-Up
Electrical Idle Reset
After Connecting RXN/RXP
After Recovered Clock Becomes Stable
After an RX Elastic Buffer Error
After Changing Channel Bonding Mode During Run Time
After a PRBS Error
After Comma Realignment
Transceiver Master Reset
Transceiver Master TX Reset in Response to Completion of Configuration
Transceiver Master RX Reset in Response to Completion of Configuration
Quad Sharing with Multiple IP Cores
Ports and Attributes
Rate Change
Rate Change Use Mode without Reference Clock Change
Rate Change Use Mode with Reference Clock Changes
Rate Change Notes
Ports and Attributes
Power Down
PLL Power Down
TX and RX Power Down
Ports and Attributes
Loopback
Ports and Attributes
Fabric Configuration Interface
Usage Model
Ports and Attributes
Digital Monitor
Ports and Attributes
Use Mode
Transmitter
TX Interface
Interface Width Configuration
TXUSRCLK Generation
Ports and Attributes
Driving the TX Interface
TX 8B/10B Encoder
TX 8B/10B Bit and Byte Ordering
K Characters
Running Disparity
Enabling and Disabling 8B/10B Encoding
Ports and Attributes
TX 128B/130B Encoder
Ports and Attributes
TX Buffer
Using the TX Buffer
Ports and Attributes
TX Buffer Bypass
Ports and Attributes
TX Buffer Bypass Use Modes
TX Buffer Bypass in Single-Lane Auto Mode without Asynchronous Gearbox
TX Buffer Bypass in Single-Lane with Asynchronous Gearbox (1:1 Mode)
TX Buffer Bypass in Single-Lane with Asynchronous Gearbox (2:1 Mode)
TX Buffer Bypass in Multi-Lane Auto Mode without Asynchronous Gearbox
TX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (1:1 Mode)
TX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (2:1 Mode)
TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Single-Lane Auto Mode with TX Master
TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Single-Lane Auto Mode with RX Master
TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode with TX Master
TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode with RX Master
TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass with Asynchronous Gearbox Mode
TX Synchronous Gearbox
Enabling the TX Synchronous Gearbox
TX Synchronous Gearbox Bit and Byte Ordering
Using the TX Synchronous Gearbox
Ports and Attributes
TX Asynchronous Gearbox
Enabling the TX Asynchronous Gearbox
TX Asynchronous Gearbox Bit and Byte Ordering
Reading Datapath Latency
Ports and Attributes
TX Pattern Generator
Ports and Attributes
Using TX Pattern Generator
TX CRC Generator
Using the CRC Generator
Ports and Attributes
TX Polarity Control
Ports and Attributes
Using TX Polarity Control
TX Fabric Clock Output Control
Serial Clock Divider
Parallel Clock Divider and Selector
TX Programmable Divider
TX DAPI and TX DAPI Bypass Dividers
Ports and Attributes
TX Phase Interpolator PPM Controller
Ports and Attributes
TX Configurable Driver
TX Driver Swing Control
TX Driver Post-Cursor Control
TX Driver Pre-Cursor Control
Ports and Attributes
TX Receiver Detect Support for PCI Express Designs
Ports and Attributes
TX Out-of-Band Signaling
Ports and Attributes
Receiver
RX Analog Front End
RX Termination and Use Modes
Ports and Attributes
RX Out-of-Band Signaling
Ports and Attributes
RX Equalizer (DFE and LPM)
Ports and Attributes
Choosing Between LPM and DFE Use Modes
LPM Use Mode
DFE Use Mode
Switching Between LPM and DFE Modes at Run Time
RX CDR
Ports and Attributes
RX CDR Lock to Reference
RX Interface
Interface Width Configuration
RXUSRCLK Generation
Ports and Attributes
RX Fabric Clock Output Control
Serial Clock Divider
Parallel Clock Divider and Selector
RX Programmable Divider
RX DAPI and RX DAPI Bypass Dividers
Ports and Attributes
RX Margin Analysis
Eye Scan Theory
Eye Scan Architecture
Ports and Attributes
RX Polarity Control
Ports and Attributes
Using RX Polarity Control
RX Pattern Checker
Ports and Attributes
RX CRC Checker
Using the CRC Checker
Ports and Attributes
RX Byte and Word Alignment
Enabling Comma Alignment
Configuring Comma Patterns
Activating Comma Alignment
Alignment Status Signals
Alignment Boundaries
Manual Alignment
Ports and Attributes
RX 8B/10B Decoder
RX 8B/10B Bit and Byte Ordering
RX Running Disparity
Special Characters
Enabling and Disabling 8B/10B Decoding
Ports and Attributes
RX 128/130B Decoder
Ports and Attributes
RX Buffer
Using the RX Phase Buffer
Ports and Attributes
RX Buffer Bypass
Ports and Attributes
RX Buffer Bypass Use Modes
RX Buffer Bypass in Single-Lane Auto Mode
RX Buffer Bypass in Multi-Lane Auto Mode
Using TX and RX Buffer Bypass with Common Clock Sharing
RX Clock Correction
Ports and Attributes
Using RX Clock Correction
Enabling Clock Correction
RX Channel Bonding
Ports and Attributes
Using RX Channel Bonding
Enabling Channel Bonding
Channel Bonding Mode
Connecting Channel Bonding Ports
Setting Channel Bonding Sequences
Setting the Maximum Skew
Precedence between Channel Bonding and Clock Correction
RX Synchronous Gearbox
Enabling the RX Synchronous Gearbox
Ports and Attributes
RX Gearbox Operating Modes
RX Gearbox Block Synchronization
RX Asynchronous Gearbox
Enabling the RX Asynchronous Gearbox
Reading Datapath Latency
Ports and Attributes
Board Design Guidelines
Pin Description and Design Guidelines
Transceiver Pin Descriptions
Termination Resistor Calibration Circuit
Reference Clock
GTY Transceiver Reference Clock Checklist
Reference Clock Interface
LVDS
LVPECL
AC Coupled Reference Clock
Unused Reference Clocks
Reference Clock Output Buffer
Reference Clock Power
Power Supply
Analog Power Supply Pins
Power Supply and Filtering
Power Up/Down and Reset on Multiple Lanes
Power Supply Regulators
Linear versus Switching Regulators
Linear Regulator
Switching Regulator
Power Supply Distribution Network Staged Decoupling
Die
Package
Printed Circuit Board
PCB Design Checklist
8B/10B Valid Characters
Additional Resources and Legal Notices
Finding Additional Documentation
Support Resources
References
Revision History
Please Read: Important Legal Notices

Back to home page