RPLL Reset

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RPLL must be reset before it can be used. Each transceiver Quad has dedicated reset ports for each of the two respective RPLLs. As shown in the following figure, RPLLRESET is an input that resets the RPLL. RPLLLOCK is an output that indicates the reset process is done. The guideline for this asynchronous RPLLRESET pulse width is one period of the reference clock. After an RPLLRESET pulse, the internal reset controller generates an internal RPLL reset followed by an internal SDM reset. The time required for the RPLL to lock is affected by a few factors, such as bandwidth setting and clock frequency.

Figure 1. RPLL Reset Timing Diagram