Reference Clock

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

This section focuses on the selection of the reference clock source or oscillator. An oscillator is characterized by:

  • Frequency range
  • Output voltage swing
  • Jitter (deterministic, random, peak-to-peak)
  • Rise and fall times
  • Supply voltage and current
  • Noise specification
  • Duty cycle and duty-cycle tolerance
  • Frequency stability

These characteristics are selection criteria when choosing an oscillator for a GTY transceiver design. Figure 1 illustrates the convention for the single-ended clock input voltage swing, peak-to-peak. This figure is provided to show the contrast to the differential clock input voltage swing calculation shown in Figure 2, as used in the GTY transceiver portion of the Versal device data sheets.

Figure 1. Single-Ended Clock Input Voltage Swing, Peak-to-Peak

The following figure illustrates the differential clock input voltage swing, which is defined as MGTREFCLKP – MGTREFCLKN.

Figure 2. Differential Clock Input Voltage Swing, Peak-to-Peak

The following figure shows the rise and fall time convention of the reference clock.

Figure 3. Rise and Fall Times

The following figure illustrates the internal details of the IBUFDS. The dedicated differential reference clock input pair MGTREFCLKP/MGTREFCLKN is internally terminated with 100Ω differential impedance. The common mode voltage of this differential reference clock input pair is either GTY_AVCC, 0.88V, or GTYP_AVCC, 0.92V. See the Versal device data sheets for exact specifications.

Figure 4. MGTREFCLK Input Buffer Details
Note: The resistor values are nominal. See the Versal device data sheets for exact specifications.