PCB Design Checklist

MGTREFCLK0N

MGTREFCLK1P

MGTREFCLK1N

• Use AC coupling capacitors for connection to oscillator.
• For AC coupling capacitors, see Reference Clock Interface.
• Reference clock oscillator output must comply with the minimum and maximum input amplitude requirements for these input pins. See the Versal device data sheets.

When configured as an output:

• Use AC coupling capacitors for connection to receiving device.
• For AC coupling capacitors use 0.01 μF.
• For output signal characteristics, see the Versal device data sheets.
• If reference pins are not used, leave the associated pin pair unconnected. However, if the IBUFDS_GTE5 is instantiated in the design but not used, the associated pin pair should be connected to GND.

CH[0/1/2/3]_GTYRXN

CH[0/1/2/3]_GTYPRXP

CH[0/1/2/3]_GTYPRXN

• Use AC coupling capacitors for connection to transmitter. The recommended value for AC coupling capacitor is 100 nF.
• Receiver data traces should be provided enough clearance to eliminate crosstalk from adjacent signals.
• If a receiver will never be used under any conditions, connect the associated pin pair to GND.
• If a receiver is not used and not connected to anything under some conditions, but might be connected to something and used under other conditions, then for the conditions when the receiver is unused, either do not instance the GTY transceiver in the Versal device design, or if the GTY transceiver is instanced, set RXPD[1:0] to 2'b11.
• See RX Analog Front End for more details.

CH[0/1/2/3]_GTYTXN

CH[0/1/2/3]_GTYPTXP

CH[0/1/2/3]_GTYPTXN

• The transmitter should be AC coupled to the receiver. The recommended value for the AC coupling capacitor is 100 nF.
• Transmitter data traces should be provided enough clearance to eliminate crosstalk from adjacent signals.
• If a transmitter is not used, leave the associated pin pair unconnected.

• Connect to GTY_AVTT and to a 100Ω resistor that is also connected to MGTRREF. Use identical trace geometry for the connection between the resistor and this pin and for the connection from the other pin of the resistor to MGTRREF. Also, the DC resistance of the PCB trace should be limited to less than 0.5Ω.
• See Termination Resistor Calibration Circuit.
• If an entire PSG is not used by any Quads, tie MGTAVTTRCAL to ground.

• Connect a 100Ω resistor that is also connected to MGTAVTTRCAL. Use identical trace geometry for the connection between the resistor and this pin and for the connection from the other pin of the resistor to MGTAVTTRCAL. Also, the DC resistance of the PCB trace should be limited to less than 0.5Ω.
• See Termination Resistor Calibration Circuit.
• If an entire PSG is not used by any Quads, tie MGTRREF to ground.

GTYP_AVCC

• The nominal voltage is 0.88 V_DC for GTY and 0.92 V_DC for GTYP.
• See the Versal device data sheets for power supply voltage tolerances.
• The power supply regulator for this voltage should not be shared with non-transceiver loads.
• Many packages have multiple groups of power supply connections in the package for GTY_AVCC and GTYP_AVCC. Information on pin locations for each package can be found in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
• For optimal performance, power supply noise must be less than 10 mVpp.
• If all of the Quads in a power supply group are not used, the associated power pins can be left unconnected or tied to GND.
• For power consumption and filter capacitor recommendations, refer to the Power Design Manager (PDM) tool (download at www.xilinx.com/power).

• The nominal voltage is 1.2 V_DC.
• See the Versal device data sheets for power supply voltage tolerances.
• The power supply regulator for this voltage should not be shared with non-transceiver loads.
• Many packages have multiple groups of power supply connections in the package for GTY_AVTT. Information on pin locations for each package can be found in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
• For optimal performance, power supply noise must be less than 10 mVpp.
• If all of the Quads in a power supply group are not used, the associated power pins can be left unconnected or tied to GND.
• For power consumption and filter capacitor recommendations, refer to the Power Design Manager (PDM) tool (download at www.xilinx.com/power).

• The nominal voltage is 1.5 V_DC.
• See the Versal device data sheets for power supply voltage tolerances.
• The power supply regulator for this voltage should not be shared with non-transceiver loads.
• Many packages have multiple groups of power supply connections in the package for GTY_AVCCAUX. Information on pin locations for each package can be found in Versal Adaptive SoC Packaging and Pinouts Architecture Manual (AM013).
• For optimal performance, power supply noise must be less than 10 mVpp.
• If all the LCPLLs in this power supply group are not used but the Quads are used, the filter capacitors are not necessary, and these pins can be connected to VCCAUX.
• If all of the Quads in a power supply group are not used, the associated power pins can be left unconnected or tied to GND.
• For power consumption and filter capacitor recommendations, refer to the Power Design Manager (PDM) tool (download at www.xilinx.com/power).