TX Interface

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The TX interface is the gateway to the TX datapath of the GTY/GTYP transceiver. Applications transmit data through the GTY/GTYP transceiver by writing data to the TXDATA port on the positive edge of TXUSRCLK. The width of the port can be configured to be two, four, or eight bytes wide. Port widths can be 16, 20, 32, 40, 64, 80, and 128. The total data width can be extended from eight byte to sixteen bytes wide by using the CH*_TXCTRL0 and CH*_TXCTRL1 ports together, which can provide 160 bits combined. The rate of the parallel clock TXUSRCLK at the interface is determined by the TX line rate, the width of the CH*_TXDATA port, and whether or not 8B/10B encoding is enabled. This section shows how to drive the parallel clock and explains the constraint on this clock for correct operation.