RX Interface

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX interface is the gateway to the RX datapath of the GTY and GTYP transceiver. Applications receive data through the GTY and GTYP transceiver by receiving data from the RXDATA port on the positive edge of RXUSRCLK. The width of the port can be configured to be two, four, or eight bytes wide. The actual width of the port depends on the RX_DATA_WIDTH and RX_INT_DATA_WIDTH attributes and whether or not 8B10B decoding is enabled. Port widths can be 16, 20, 32, 40, 64, 80, and 128 bits. The CH*_RXTRL0 and CH*_RXTRL1 ports must be used together to extend the width from 128 to 160 bits. The rate of the parallel clock (RXUSRCLK) at the interface is determined by the RX line rate, the width of the RXDATA port, and whether or not 8B/10B decoding is enabled. This section shows how to drive the parallel clocks and explains the constraints on those clocks for correct operation. The highest transmitter data rates require an 8-byte interface to achieve an RXUSRCLK rate in the specified operating range.