TXUSRCLK Generation

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
Release Date
1.3 English

The TX interface includes the parallel clock TXUSRCLK. The required rate for TXUSRCLK depends on the interface width of the GTYE5_QUAD and GTYP_QUAD primitives and the TX line rate of the GTY/GTYP transmitter. Figure 1 shows how to calculate the required rate for TXUSRCLK for all cases except when the TX asynchronous gearbox is enabled. In the equation, interface width refers to the TX_DATA_WIDTH.

Figure 1. TXUSRCLK

TXUSRCLK is the internal synchronization clock for all signals into the TX side of the GTY/GTYP transceiver. Most signals into the TX side of the GTY/GTYP transceiver are sampled on the positive edge of TXUSRCLK.