Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

This chapter shows how to configure and use each of the functional blocks inside the transmitter (TX). Each transceiver includes an independent transmitter, which consists of a PCS and a PMA. The following figure shows the functional blocks of the transmitter. Parallel data flows from the device logic into the TX interface, through the PCS and PMA, and then out the TX driver as high-speed serial data.

Figure 1. Transceiver TX Block Diagram

The key elements within the transceiver TX are:

  1. TX Interface
  2. TX 8B/10B Encoder
  3. TX Synchronous Gearbox
  4. TX Buffer
  5. TX Buffer Bypass
  6. TX Pattern Generator
  7. TX Polarity Control
  8. TX Fabric Clock Output Control
  9. TX Phase Interpolator PPM Controller
  10. TX Configurable Driver
  11. TX Out-of-Band Signaling