Transceiver TX Reset in Response to GTTXRESET Pulse in Full Sequential Reset

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The GTY and GTYP transceiver allows you to reset the entire TX completely at any time by sending GTTXRESET and PCSRSVDIN[7] (TXDAPIRESET) an active-High pulse. These conditions must be met when using GTTXRESET:

  1. TXRESETMODE must be set to sequential mode.
  2. All TXPMARESETMASK, PCSRSVDIN[6:5] (TXDAPIRESETMASK), and TXPCSRESETMASK bits should be held High during the reset sequence before TXRESETDONE is detected High.
  3. The associated PLL must indicate locked.
  4. The guideline for this asynchronous GTTXRESET pulse width is one period of the reference clock.
Figure 1. Transmitter Reset after GTTXRESET Pulse in Full Sequential Reset