Reference Clock Output Buffer

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The reference clock pins can be configured to be output pins that drive an RX recovered clock from one of the transceivers in the Quad. Operation and configuration of this buffer is discussed in Reference Clock Input/Output Structure. This output is designed to supply a signal through DC blocking capacitors on the PCB. The signal levels are comparable to those of LVDS after the DC blocking capacitors. See the Versal device data sheets for output levels.

Figure 1. Versal Architecture GTY Transceiver Reference Clock Output Connection