PLL Power Down

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

To activate the LCPLL power-down mode, the active-High HSCLK*_LCPLLPD signal is asserted. Similarly, to activate the RPLL power-down mode, the active-High HSCLK*_RPLLPD signal is asserted. When either HSCLK*_LCPLLPD or HSCLK*_RPLLPD is asserted, the corresponding PLL is powered down. As a result, all clocks derived from the respective PLL are stopped.

Recovery from this power state is indicated by the assertion of the corresponding PLL lock signal that is either the HSCLK*_LCPLLLOCK signal of the LCPLL or the HSCLK*_RPLLLOCK signal of the RPLL.