Power Supply and Filtering

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The GTY and GTYP transceivers Quad requires three analog power supplies: GTY_AVCC at a nominal voltage level of 0.88 VDC or 0.92VDC for GTYP_AVCC, GTY_AVCCAUX at a nominal voltage level of 1.5 VDC, and GTY_AVTT at a nominal voltage level of 1.2 VDC for Versal adaptive SoCs. The pins for each of these analog power supplies are tied to a plane in the package. In some packages, there are two planes (a left plane and a right plane) for each of the analog power supplies. See Board Design Guidelines for a discussion of the internal power planes in the GTY transceiver packages.

Noise on the GTY transceiver analog power supplies can cause degradation in the performance of the transceivers. The most likely form of degradation is an increase in jitter at the output of the GTY transmitter and reduced jitter tolerance in the receiver. Sources of power supply noise are:

  • Power supply regulator noise
  • Power distribution network
  • Coupling from other circuits

Each of these noise sources must be considered in the design and implementation of the GTY transceiver analog power supplies. The total peak-to-peak noise as measured at the input pin of the Versal adaptive SoC should not exceed 10 mVpp.