In multi-lane with asynchronous gearbox mode with TX and RX common clock, the RX/TXUSRCLK domain is used to drive logic in the RX/TXPHYCLK domain. The following figure shows an example of asynchronous mode common clock buffer bypass lanes.
When the TX/RX internal data width is identical to the fabric interface data width, the TX/RX buffer is directly bypassed. Use these transceiver settings to bypass the RX and TX buffer with asynchronous gearbox in common clock multi-lane 1:1 mode:
Common clock settings:
- CH*_RX_PHALIGN_CFG5[27:26] =
2'b00(CMN_FAB_CLK_PHALIGN_MODE) (Disabled because each lane works individually)
TX buffer bypass settings:
- CH*_TX_PHALIGN_CFG0[31] =
1'b0(DLY_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[30] =
1'b0(PH_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) (All lanes are configured as slaves in multi-lane asynchronous gearbox mode) - CH*_TX_PHALIGN_CFG0[15] =
1'b1(SYNC_MULTI_LANE) - CH*_TX_PHALIGN_CFG0[14] =
1'b1(TXBUF_BYPASS_MODE) - CH*_TX_PHALIGN_CFG1[2:1] =
2'b00(CHAIN_MODE) - CH*_TX_PHALIGN_CFG1[0] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[2:0] =
3'b011or3'b101(TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK
RX buffer bypass settings:
- CH*_RX_PHALIGN_CFG0[31] =
1'b0(DLY_ALIGN_EN) - CH*_RX_PHALIGN_CFG0[30] =
1'b0(PH_ALIGN_EN) - CH*_RX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) (All lanes are configured as slaves in multi-lane asynchronous gearbox mode) - CH*_RX_PHALIGN_CFG0[15] =
1'b1(SYNC_MULTI_LANE) - CH*_RX_PHALIGN_CFG0[14] =
1'b1(RXBUF_BYPASS_MODE) - CH*_RX_PHALIGN_CFG1[3:2] =
2'b00(CHAIN_MODE) - CH*_RX_PHALIGN_CFG1[1] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[14:12] =
3'b110to select TXOUTCLK as source of RXOUTCLK
In RX and TX buffer bypass with asynchronous gearbox in common clock multi-lane 1:1 mode, because the asynchronous gearbox FIFO provides the phase compensation, there is no need to perform the phase alignment procedure.
When the TX/RX fabric interface data width is twice the internal data width, the TX/RX buffer is bypassed through the 2:1 REG. Use these transceiver settings to bypass the RX and TX buffer with asynchronous gearbox in common clock multi-lane 2:1 mode:
Common clock settings:
- CH*_RX_PHALIGN_CFG5[27:26] =
2'b00(CMN_FAB_CLK_PHALIGN_MODE) (Disabled because each lane works individually)
TX buffer bypass settings:
- CH*_TX_PHALIGN_CFG0[31] =
1'b1(DLY_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[30] =
1'b1(PH_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) (All lanes are configured as slaves in multi-lane asynchronous gearbox mode) - CH*_TX_PHALIGN_CFG0[15] =
1'b1(SYNC_MULTI_LANE) - CH*_TX_PHALIGN_CFG0[14] =
1'b1(TXBUF_BYPASS_MODE) - CH*_TX_PHALIGN_CFG1[2:1] =
2'b00(CHAIN_MODE) - CH*_TX_PHALIGN_CFG1[0] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[2:0] =
3'b011or3'b101(TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK.
RX buffer bypass settings:
- CH*_RX_PHALIGN_CFG0[31] =
1'b1(DLY_ALIGN_EN) - CH*_RX_PHALIGN_CFG0[30] =
1'b1(PH_ALIGN_EN) - CH*_RX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) (All lanes are configured as slaves in multi-lane asynchronous gearbox mode) - CH*_RX_PHALIGN_CFG0[15] =
1'b1(SYNC_MULTI_LANE) - CH*_RX_PHALIGN_CFG0[14] =
1'b1(RXBUF_BYPASS_MODE) - CH*_RX_PHALIGN_CFG1[3:2] =
2'b00(CHAIN_MODE) - CH*_RX_PHALIGN_CFG1[1] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[14:12] =
3'b110to select TXOUTCLK as source of RXOUTCLK
When bypassing the RX and TX buffer with asynchronous gearbox in common clock multi-lane 2:1 mode, the following timing diagram shows the required steps to perform auto phase and delay alignment.
Notes relevant to the figure:
- The sequence of events in the figure is not drawn to scale.
- CH[Lane *]_* denotes ports of various lanes.
- After conditions such as a reset or rate change, common clock phase alignment must be performed. The common clock phase and delay alignments are initiated by asserting CH*_TXPHDLYRESET and CH*_RXPHDLYRESET.
- Common clock phase alignment is done when the rising edge of CH*_TXSYNCDONE and CH*_RXSYNCDONE for every lane is detected. This signal should remain asserted until another alignment procedure is initiated.
- An assertion/deassertion of GTTXRESET and GTRXRESET is required if CH*_TXSYNCDONE and CH*_RXSYNCDONE for every lane does follow the sequence shown in the figure.
- Common clock delay alignment continues to adjust RX/TXUSRCLK to compensate for temperature and voltage variations.