RX Synchronous Gearbox

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX synchronous gearbox provides support for 64B/66B and 64B/67B header and payload separation. The gearbox uses output pins CH*_RXDATA[127:0] and CH*_RXHEADER[5:0] for the payload and header of the received data in normal mode. Similar to TX Synchronous Gearbox, the RX synchronous gearbox operates with the PMA using a single clock. Because of this, occasionally, the output data is invalid. Output pins CH*_RXHEADERVALID and CH*_RXDATAVALID determine if the appropriate header and data are valid. The RX synchronous gearbox supports 2-byte, 4-byte, 8-byte, and 16-byte interfaces.

The data out of the RX synchronous gearbox is not necessarily aligned. Alignment is done in the interconnect logic. The CH*_RXGEARBOXSLIP port can be used to slip the data from the gearbox cycle-by-cycle until correct alignment is reached. It takes a specific number of cycles before the bitslip operation is processed and the output data is stable. Descrambling of the data and block synchronization is done in the interconnect logic.