Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

It is a common practice to define the location of transceiver Quads early in the design process to ensure correct usage of clock resources and to facilitate signal integrity analysis during board design. The implementation flow facilitates this practice through the use of location constraints in the XDC file.

The position of each transceiver Quad primitive is specified by an XY coordinate system that describes the column number and the relative position within that column.

Use the I/O planner in the Vivado I/O planner to set the transceiver locations and be modified manually to change the placement locations. Care must be taken to ensure that all of the parameters needed to configure the transceivers are correctly entered.