The TX phase alignment circuit is used to adjust the phase difference between the PCS parallel clock domain (PHYCLK) and the TXUSRCLK domain when the TX buffer is bypassed. It also performs the TX delay alignment by continuously adjusting the TXUSRCLK to compensate for the temperature and voltage variations. The combined TX phase and delay alignments can be automatically performed by the GTY/GTYP transceiver. Refer to Table 1 for trade-offs between buffering and phase alignment. The following figure shows how TX phase alignment allows the TX buffer to be bypassed. Before TX phase alignment, there is no guaranteed phase relationship between the PCS parallel clock domain (PHYCLK) and the TXUSRCLK domain.
