In single-lane with asynchronous gearbox mode, the TXUSRCLK domain is used to drive logic in the TXPHYCLK domain. When the TX fabric interface data width is twice the internal data width, the TX buffer is bypassed through the 2:1 REG. The 2:1 REG requires the phase alignment procedure to be performed identical to Figure 1. In this use case, note that the latency is still deterministic because the continuous phase alignment at 2:1 REG does not impact the data latency through the data path.
Figure 1. TX Buffer Bypass in Single-Lane with Asynchronous Gearbox 2:1
Mode
Use these transceiver settings to bypass the TX buffer with asynchronous gearbox enabled in single-lane 2:1 mode:
- CH*_TX_PCS_CFG0[5] =
1'b1(USE_BG) - CH*_TX_PHALIGN_CFG0[31] =
1'b1(DLY_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[30] =
1'b1(PH_ALIGN_EN) - CH*_TX_PHALIGN_CFG0[17:16] =
2'b00(SYNC_MODE) - CH*_TX_PHALIGN_CFG0[15] =
1'b0(SYNC_MULTI_LANE) - CH*_TX_PHALIGN_CFG0[14] =
1'b1(TXBUF_BYPASS_MODE) - CH*_TX_PHALIGN_CFG1[2:1] =
2'b00(CHAIN_MODE) - CH*_TX_PHALIGN_CFG1[0] =
1'b1(ASYNC_GBOX_PHALIGN_EN) - CH*_PIPE_CTRL_CFG7[2:0] =
3'b011or3'b101(TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK