TX Synchronous Gearbox Bit and Byte Ordering

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

For both 64B/66B and 64B/67B encoding, bit transmission sends the LSB first and ends with the MSB. The following figure shows an example of the first four cycles of data entering and exiting the TX gearbox for 64B/66B encoding when using a 4-byte logic interface (TX_DATA_WIDTH = 32 (4-byte), TX_INT_DATAWIDTH = 1 (4-byte)) in normal mode (CH*_TX_PCS_CFG0[2] = 1'b0). The input consists of a 2-bit header and 32 bits of data. On the first cycle, the header and 30 bits of data exit the TX gearbox. On the second cycle, the remaining two data bits from the previous cycle’s TXDATA input along with 30 data bits from the current TXDATA input exit the TX gearbox. On the third cycle, the output of the TX gearbox contains two remaining data bits from the first 66-bit block, the header of the second 66-bit block, and 28 data bits from the second 66-bit block.

Figure 1. TX Gearbox Bit Ordering in Normal Mode (CH*_TX_PCS_CFG0[2] = 1’b0)

Note relevant to the figure:

  1. Per IEEE802.3ae nomenclature, H1 corresponds to TxB<0>, H0 to TxB<1>, etc.