RX Buffer Bypass

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX phase alignment circuit is used to adjust the phase difference between the PCS parallel clock domain (PHYCLK) and the RXUSRCLK domain when the RX elastic buffer is bypassed. It also performs the RX delay alignment by adjusting RXUSRCLK to compensate for temperature and voltage variations. The combined RX phase and delay alignments can be automatically performed by the GTY and GTYP transceivers. Table 1 shows trade-offs between buffering and phase alignment.

The RX buffer can be bypassed to reduce latency when the RX recovered clock is used to source RXUSRCLK. When the RX buffer is bypassed, latency through the RX datapath is low and deterministic.

The following figure shows how RX phase alignment allows the RX elastic buffer to be bypassed. Before RX phase alignment, there is no guaranteed phase relationship between the PCS parallel clock domain (PHYCLK) and the RXUSRCLK domain. RX phase alignment selects a phase shifted version of the RX recovered clock from the CDR so that there is no significant phase difference between PHYCLK and RXUSRCLK.

Figure 1. RX Buffer Bypass
Note: In order to use multi-lane buffer bypass, the Quad placement must be contiguous.