TX Buffer Bypass in Multi-Lane Auto Mode without Asynchronous Gearbox

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

When a multi-lane application requires TX buffer bypass, phase alignment is performed automatically. This section describes the steps required to perform the multi-lane TX buffer bypass alignment procedure automatically.

  • Initial Master: In a multi-lane application, the buffer bypass initial master is the lane that is the source of the TXOUTCLK.
    • CH*_TX_PHALIGN_CFG0[17:16] = 2'b01 (SYNC_MODE)
  • Maintenance Master: This lane shares the same TXUSRCLK generated from the TXOUCLK of the buffer bypass initial master. The maintenance master also provides delay skew information, which is forwarded internally to the initial master lane.
    • CH*_TX_PHALIGN_CFG0[17:16] = 2'b10 (SYNC_MODE)
  • Slave: These are all the lanes that share the same TXUSRCLK, which is generated from the TXOUCLK of the buffer bypass initial master.
    • CH*_TX_PHALIGN_CFG0[17:16] = 2'b00 (SYNC_MODE)

The following figure shows an example of buffer bypass initial master, maintenance master, and slave lanes.

Figure 1. TX Buffer Bypass Initial Master, Maintenance Master, and Slave Lanes

Use these transceiver settings to bypass the TX buffer in multi-lane mode:

  • CH*_TX_PHALIGN_CFG0[31] = 1'b1 (DLY_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[30] = 1'b1 (PH_ALIGN_EN)
  • CH*_TX_PHALIGN_CFG0[15] = 1'b1 (SYNC_MULTI_LANE)
  • CH*_TX_PHALIGN_CFG0[14] = 1'b1 (TXBUF_BYPASS_MODE)
  • CH*_TX_PHALIGN_CFG1[0] = 1'b0 (ASYNC_GBOX_PHALIGN_EN)
  • CH*_PIPE_CTRL_CFG7[2:0] = 3'b011 or 3'b101 (TXOUTCLKCTL) to select either the transceiver reference clock or the programmable divider clock as the source of TXOUTCLK.

Multi-lane buffer bypass must only be used on lanes that have physical locations that are directly adjacent to one another. CH*_TX_PHALIGN_CFG1[2:1] (CHAIN_MODE) must be set according to the physical location of the multi-lane group.

  • Top location: CH*_TX_PHALIGN_CFG1[2:1] = 2'b01 (CHAIN_MODE)
  • Middle location(s): CH*_TX_PHALIGN_CFG1[2:1] = 2'b11 (CHAIN_MODE)
  • Bottom location: CH*_TX_PHALIGN_CFG1[2:1] = 2'b10 (CHAIN_MODE)

The following figure shows the required steps to perform auto TX phase and delay alignment.

Figure 2. TX Buffer Bypass—Multi-Lane Auto Mode

Notes relevant to the figure:

  1. The sequence of events in the figure is not drawn to scale.
  2. CH[IM]_* denotes ports related to the initial master lane.
  3. CH[MM]_* denotes ports related to the maintenance master lane.
  4. CH[S]_* denotes ports related to the slave lane(s).
  5. After conditions such as a transmitter reset or TX rate change, TX phase alignment must be performed to align TXPHYCLK and TXUSRCLK. The TX phase and delay alignments are initiated by asserting CH*_TXPHDLYRESET.
  6. TX phase alignment is done when the rising edge of CH[IM]_TXSYNCDONE is detected. This signal should remain asserted until another alignment procedure is initiated.
  7. An assertion/deassertion of GTTXRESET is required if CH[IM]_TXSYNCDONE does not follow the sequence shown in the figure.
  8. TX delay alignment continues to adjust TXUSRCLK to compensate for the temperature and voltage variations.