Ring PLL

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Each GTY/GTYP transceiver Quad contains two ring-based channel PLLs (RPLL), one RPLL in each of the HSCLK0/1 block. The internal channel clocking architecture is shown in the following figure. The TX and RX clock dividers can individually select the clock from the RPLL or LCPLL assigned to that particular channel to allow the TX and RX datapaths to operate at asynchronous frequencies using different reference clock inputs.

Figure 1. Channel Clocking Architecture

The RPLL input clock selection is described in Reference Clock Selection and Distribution. The RPLL outputs feed the TX and RX clock divider blocks, which control the generation of serial and parallel clocks used by the PMA and PCS blocks. The RPLL can be shared between the TX and RX datapaths if they operate at line rates that are integral multiples of the same VCO frequency, with the limitation that the RPLL from HSCLK0 can only drive channel 0/1 and RPLL from HSCLK1 can only drive channel 2/3.

The following figure illustrates a conceptual view of the RPLL architecture. The input clock is divided by a factor of M before feeding into the phase frequency detector. The feedback divider, N, determines the VCO multiplication ratio and the RPLL output frequency. When the fractional feature of the feedback divider N is enabled, its effective ratio becomes a combination of the N factor plus a fractional part.

Important: The fractional-N feature of the RPLL is designed specifically to provide a clocking source and when enabled, the output of the RPLL must not be used to drive the actual datapath (PMA or PCS) of the transceiver channel.

A number of lock indicators are generated, and the RPLL lock compares the frequencies of the reference clock and the VCO feedback clock to determine if a frequency lock has been achieved.

Figure 2. RPLL Block Diagram

The RPLL has a nominal VCO operating range between 4.0 GHz to 8.0 GHz. For additional information regarding the exact RPLL operating range for different device speed grades, refer to the Versal device data sheets. The Versal Adaptive SoC Transceivers Wizard chooses the appropriate RPLL settings based on application requirements.

The following equation shows how to determine the RPLL output frequency (GHz).

Figure 3. RPLL Output Frequency

The following equation shows how to determine the line rate (Gb/s). D represents the value of the TX or RX clock divider block in the channel.

Figure 4. Line Rate

The following equation shows how to determine the fractional part of the feedback divider presented in Figure 3.

Figure 5. Fraction Part

The following table lists the allowable divider settings for RPLL.

Table 1. RPLL Divider Settings
Factor Attribute/Port Valid Settings
M RPLL_REFDIV Valid settings are 1, 2, 3, 4.



The valid divider range from the integer N depends on whether or not the fractional component is enabled, and also whether the RPLL is used for clock generation or driving the transceiver datapath.

Fractional component disabled: 5–25, 80

Fractional component enabled or fabric clocking: 8–80

The fractional component that is read or written in the register is N – 2. For N = 80, the value of N is 78.

When the fractional part is used or if the RPLL output will not drive the datapath, the RPLL is used as a clocking source where the output can be routed to the fabric only. It cannot be used to drive the transceiver datapath (PCS or PMA) in this use model.




1, 2, 4, 8, 16


0 – (224 – 1)