TX Pattern Generator

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Pseudo-random bit sequences (PRBS) are commonly used to test the signal integrity of high-speed links. These sequences appear random but have specific properties that can be used to measure the quality of a link. The GTY/GTYP transceiver pattern generator block can generate several industry-standard PRBS patterns listed in the following table.

Table 1. Supported PRBS Patterns
Name Polynomial Length of Sequence Description
PRBS-7 1 + X6 + X7 27 – 1 bits Used to test channels with 8B/10B.
PRBS-9 1 + X5 + X9 29 – 1 bits ITU-T Recommendation O.150, Section 5.1. PRBS-9 is one of the recommended test partterns for SFP+.
PRBS-15 1 + X14 + X15 215 – 1 bits ITU-T Recommendation O.150, Section 5.3. PRBS-15 is often used for jitter measurement because it is the longest pattern that the Keysight DCA-X sampling oscilloscope can handle.
PRBS-23 1 + X18 + X23 223 – 1 bits ITU-T Recommendation O.150, Section 5.6. PRBS-23 is often used for non-8B/10B encoding schemes. It is one of the recommended test patterns in the SONET specification.
PRBS-31 1 + X28 + X31 231 – 1 bits ITU-T Recommendation O.150, Section 5.8. PRBS-31 is often used for non-8B/10B encoding schemes. It is a recommended PRBS test pattern for 10 Gigabit Ethernet. See IEEE Std 802.3ae-2002.

In addition to PRBS patterns, the transceiver supports 16 UI, 20 UI, 32 UI, 40 UI, 64 UI, or 80 UI square wave test patterns, depending on internal data width, as well as a 2 UI square wave test pattern and PCI Express compliance pattern generation. Clocking patterns are usually used to check PLL random jitter often done with a spectrum analyzer.

Table 2. PCI Express Compliance Pattern
Symbol K28.5 D21.5 K28.5 D21.5
Disparity 0 1 1 0
Pattern 0011111010 1010101010 1100000101 0101010101
Figure 1. 20 UI Square Wave

The error insertion function is supported to verify link connection and also for jitter tolerance tests. When an inverted PRBS pattern is necessary, the CH*_TXPOLARITY signal is used to control polarity.

Figure 2. TX Pattern Generator Block

The pattern generator might control when an injection of an error in the generated pattern occurs by choosing between two modes. In LEVEL mode, the generator injects an error after any cycle in which CH*_TXPRBSFORCEERR is High. In EDGE mode, an error is injected only after CH*_TXPRBSFORCEERR has just gone High after being Low in the previous cycle. The following figure shows the error injection in both operating modes.

Figure 3. LEVEL and EDGE Mode Error Injection