RXUSRCLK Generation

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX interface includes the parallel clock: RXUSRCLK. RXUSRCLK is the internal clock for the PCS logic in the transmitter. The required rate for RXUSRCLK depends on the interface width of the GTYE5_QUAD or GTYP_QUAD primitive and the RX line rate of the GTY or GTYP transmitter. The following equation shows how to calculate the required rate for RXUSRCLK for all cases except when the RX asynchronous gearbox is used. In the equation, interface width refers to the RX_DATA_WIDTH.

Figure 1. RXUSRCLK

RXUSRCLK is the main synchronization clock for all signals into the RX side of the GTY or GTYP transceiver. Most signals into the RX side of the GTY or GTYP transceiver are sampled on the positive edge of RXUSRCLK. Above a given line rate, use of the 4-byte or 8-byte internal datapath is required. For details per speed grade, refer to the Versal device data sheets.