The following table shows the revision history for this document.
Section | Revision Summary |
---|---|
10/26/2023 Version 1.3 | |
Table 2 | Removed RXRECCLK_SEL attribute. |
Table 2 | Added REFCLK0_REFCLK_EN_DRV and REFCLK1_REFCLK_EN_DRV attributes. |
Figure 2 | Corrected HSCLK1_RPLLGTREFCLK0/1 connections. |
Table 1 | Added description of how N.FractionalPart is interpreted in the register. |
Table 1 |
|
Reset Modes | Removed sentence about completion of single mode reset. |
TX Initialization and Reset and Transceiver TX Component Reset | Added sentence about TXRESETDONE not asserting in single mode. |
RX Initialization and Reset | Added sentence about RXRESETDONE not asserting in single mode. |
Transceiver RX Component Reset | Added sentence about RXRESETDONE port not being asserted in single mode. |
Transceiver Master Reset | Added description of TX/RXRESETDONE signals. |
Ports and Attributes | Added information about rate change attributes. |
Loopback | Added information about far-end PMA and far-end PCS loopback modes. |
Fabric Configuration Interface | Added sentence about using Versal Adaptive SoC Transceivers Wizard. |
Usage Model | Added section. |
Driving the TX Interface | Added bullet about TXOUTCLK. |
TXUSRCLK Generation and RXUSRCLK Generation | Added clarification of interface width. |
TX 128B/130B Encoder | Clarified 128B/130B encoder support. |
TX Buffer Bypass in Single-Lane Auto Mode without Asynchronous Gearbox, TX Buffer Bypass in Single-Lane with Asynchronous Gearbox (1:1 Mode), TX Buffer Bypass in Single-Lane with Asynchronous Gearbox (2:1 Mode), TX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (1:1 Mode), TX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (2:1 Mode), TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Single-Lane Auto Mode with TX Master, TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Single-Lane Auto Mode with RX Master, TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode with TX Master, TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass in Multi-Lane Auto Mode with RX Master, and TXUSRCLK and RXUSRCLK Sharing Using Both TX and RX Buffer Bypass with Asynchronous Gearbox Mode | Removed 3'b100 for TXOUTCLKCTL. |
TX Buffer Bypass in Multi-Lane Auto Mode without Asynchronous Gearbox |
|
TX Synchronous Gearbox Bit and Byte Ordering | Clarified order of bit transmission. |
Using the TX Synchronous Gearbox | Added section. |
Figure 1 | Updated figure. |
Table 3 | Updated eye scan masks. |
RX Pattern Checker | Clarified order in which to read error counter and cycle counter. |
Configuring Comma Patterns | Clarified commas in RAW data mode. |
Manual Alignment | Added section. |
RX 128/130B Decoder | Clarified 128B/130B usage. |
Enabling Clock Correction | Added description of enabling FIFO and clock correction support. |
Ports and Attributes | Added note about RXCHBONDLEVEL, RXCHBONDMASTER, and RXCHBONDSLAVE ports. |
Enabling Channel Bonding | Added description of enabling FIFO. |
Channel Bonding Mode, Connecting Channel Bonding Ports, Setting Channel Bonding Sequences, Setting the Maximum Skew, Precedence between Channel Bonding and Clock Correction, RX Gearbox Operating Modes, and RX Gearbox Block Synchronization | Added sections. |
Analog Power Supply Pins | Updated description of RCAL master. |
Transceiver Pin Descriptions |
|
Reference Clock, Power Supply and Filtering, and PCB Design Checklist | Added GTYP_AVCC. |
05/05/2021 Version 1.2 | |
Table 1 | Updated CEB description. |
Table 1 | Updated CEB description. |
Reference Clock Selection and Distribution | Removed restriction on reference clock sharing and made it available for all supported line rates. |
Table 1 and Table 1 | Removed div 2.5 support and table note. |
LC-Tank PLL | Updated restriction for fractional-N from 28.1 Gb/s to 30.5 Gb/s. |
Table 1 | Updated fractional component enabled settings for N.FractionalPart. |
Ports and Attributes | Added power down attributes table. |
Digital Monitor | Updated description of enabling digital monitor. |
Use Mode | Added new section. |
Using TX Pattern Generator |
|
Table 1 | Updated swing values based on production silicon characterization. |
Table 1 | Updated post-cursor de-emphasis values based on production silicon characterization. |
Table 1 | Updated pre-cursor de-emphasis values based on production silicon characterization. |
RX Buffer Bypass Use Modes | Removed RX Buffer Bypass Use Modes with Asynchronous Gearbox table. |
Ports and Attributes and Choosing Between LPM and DFE Use Modes | Added new sections. |
Switching Between LPM and DFE Modes at Run Time | Updated section. |
Table 1 | Added table. |
RX Buffer Bypass in Single-Lane with Asynchronous Gearbox (1:1 Mode), RX Buffer Bypass in Single-Lane with Asynchronous Gearbox (2:1 Mode), RX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (1:1 Mode), and RX Buffer Bypass in Multi-Lane Auto Mode with Asynchronous Gearbox (2:1 Mode) | Removed topics. |
Table 1 | Added table notes. |
Table 1 and Table 1 | Updated GTY and GTYP pad pin names based on latest primitive. |
11/24/2020 Version 1.1 | |
General updates |
|
Table 1 | Changed SIM_DEVICE to SIM_VERSION. |
Table 2 | Removed REFCLK_CTL_DRV_SWING and REFCLK_EN_DRV attributes. |
Figure 1 | Split GTREFCLKP1/0 outputs. |
Table 1 | Added RXRECCLKSEL[1:0], HSCLK0_RXRECCLK_SEL[1:0], and HSCLK1_RXRECCLK_SEL[1:0] ports. |
Figure 2 | Updated HSCLK1_RPLLGTREFCLK1/0 connections. |
Table 1 | Updated description of HSCLK[0/1]_LCPLLREFCLKSEL[2:0]. |
Table 2 | Updated description of HS1_RPLL_IPS_REFCLK_SEL. |
Table 1 | Updated description of HSCLK[0/1]_RPLLREFCLKSEL[2:0]. |
Reset and Initialization | Added note about resets being executed using Versal Adaptive SoC Transceivers Wizard. |
Loopback | Added additional requirements for near-end PCS loopback mode. |
Figure 1, Figure 93, Figure 94, and Figure 100 | Removed 64B/66B rate adaptation and encoder blocks. |
Table 1 | In recommendation for MGTREFCLK, replaced IBUFDS_GTE3/4 with IBUFDS_GTE5. |
07/16/2020 Version 1.0 | |
Initial release. | N/A |