After Recovered Clock Becomes Stable

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
Release Date
1.3 English

Depending on the design of the clocking scheme, it is possible for the RX reset sequence to be completed before the CDR is locked to the incoming data. In this case, the recovered clock might not be stable when RXRESETDONE is asserted. When the RX PCS is used, a single mode reset targeting the RX elastic buffer must be triggered after the recovered clock becomes stable.

When RX buffer bypass is used, the alignment procedure should not start until the recovered clock becomes stable.

Refer to the Versal device data sheets for successful CDR lock-to-data criteria.