Enabling the TX Synchronous Gearbox - AM002

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)
Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The following table describes the attribute settings to enable the TX synchronous gearbox.

Table 1. Enabling the TX Synchronous Gearbox
Attribute Label Description
CH*_TX_PCS_CFG0[5] USE_GB This bit must be set to 1'b1.
CH*_TX_PCS_CFG0[4:0] MODE

Bit[4] - Must be set to 1'b0.

Bit[3] - Reserved. Must be set to 1'b0.

Bit[2] - Reserved. Must be set to 1'b0.

Bit[1] - Reserved. Must be set to 1'b0.

Bit[0] - Set to 1'b0 to use 64B/67B gearbox or 1'b1 to use 64B/66B gearbox.