Reset and Initialization

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

The transceiver must be initialized after device power-up and configuration before it can be used. The transmitter (TX) and receiver (RX) can be initialized independently and in parallel as shown in the following figure. Transceiver TX and RX initialization comprises three steps:

  1. Initializing the associated PLL driving TX/RX
  2. Initializing the associated ILO
  3. Initializing the TX and RX datapaths (PMA, DAPI, Buffer Bypass, PCS)
Important: The RX datapath reset signals must be executed through the Versal Adaptive SoC Transceivers Wizard. See Versal Adaptive SoC Transceivers Wizard LogiCORE IP Product Guide (PG331).

Transceiver TX and RX can receive a clock from either the LCPLL or the RPLL. The associated PLL (LCPLL/RPLL) used by the TX and RX must be initialized first before ILO, TX and RX initialization. The ILO must be initialized after the associated PLL is locked. Any PLL and ILO used by the TX and RX is reset individually and its reset operation is completely independent from all TX and RX resets. The TX and RX datapaths must be initialized only after the associated PLL and ILO is locked.

For the GTY/GTYP transceivers, there is a master reset controller available that can run through all reset steps described above automatically. When using the master reset, the associated PLL, ILO, and TX and RX datapaths are reset in the proper sequence by toggling the respective TX and RX master reset signal.

Important: The reference clock to the transceiver must be available and stable prior to start of device programming or start of any manual reset sequence.
Figure 1. Transceiver Initialization Overview

The transceiver TX and RX use a state machine to control the initialization process. They are partitioned into a few reset regions. The partition allows the reset state machine to control the reset process in a sequence that the PMA can be reset first and the PCS can be reset after the assertion of the TXUSERRDY or RXUSERRDY. It also allows the PMA, the PCS, and functional blocks inside them to be reset individually when needed during normal operation.

The transceiver offers two types of reset: initialization and component.

  • Initialization Reset: This reset is used for complete transceiver initialization. It must be used after device power-up and configuration. During normal operation, when necessary, GTTXRESET and GTRXRESET can also be used to reinitialize the transceiver TX and RX. GTTXRESET is the initialization reset port for the transceiver TX. GTRXRESET is the initialization reset port for the transceiver RX. During initialization reset, TXRESETMODE and RXRESETMODE should be set to sequential mode. All TX PMA, TX PCS, RX PMA, and RX PCS component resets should be enabled by setting all required component bits of TXPMARESETMASK, TXPCSRESETMASK, RXPMARESETMASK, and RXPCSRESETMASK to High.
  • Component Reset: This reset is used for special cases and specific subsection resets while the transceiver is in normal operation. The component that is required to be reset is selected by setting the associated bit within TXPMARESETMASK, TXPCSRESETMASK, RXPMARESETMASK, or RXPCSRESETMASK to High. A TX component reset is triggered by toggling the GTTXRESET port. An RX component reset is triggered by toggling the GTRXRESET port. Separate component reset ports are available. These include EYESCANRESET, RXOOBRESET, RXCDRRESET, and RXPRBSCNTRESET.

All reset ports described in this section initiate the internal reset state machine when driven High. The internal reset state machines are held in the reset state until these same reset ports are driven Low. These resets are all asynchronous. The guideline for the pulse width of these asynchronous resets is one period of the reference clock, unless otherwise noted.

Note: Do not use reset ports for the purpose of power down. For details on proper power-down usage, refer to Power Down.