The TX programmable divider shown in TX Fabric Clock Output Control uses
one of the PLL output clocks to generate a parallel output
clock. By using the transceiver PLL, TX programmable
divider, and BUFG_GT, CH*_TXOUTCLK (TXOUTCLKSEL = 101) can be used as a
clock source for the interconnect logic. The supported
divider values are 4, 5, 5.5, 8, 10, 16, 16.5, 20, 32, 33,
and 40.
The high-speed clock multiplexer controlled by TX_PROGCLK_SEL is set based on the application requirements:
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00: The post TX phase interpolator (PI) clock path can be used to generate a parallel clock with a certain ppm offset created by the TX PI. In this use case, one transceiver PLL is shared for the datapath and clock generation path. The clock signal is interrupted if the channel or the source PLL is being reset. -
01: The pre TX PI clock path can be used to generate a system clock to support applications where minimal or fixed latency is needed. In this use case, one transceiver PLL is shared for the datapath and clock generation path. The clock signal is interrupted only if the source PLL is being reset. -
10: In applications where the LCPLL clock might be interrupted during reconfiguration, the bypass clock path provides the flexibility to use the RPLL to generate a stable parallel clock for the interconnect logic.