GTY Transceiver Reference Clock Checklist

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

Document ID
AM002
Release Date
2023-10-26
Revision
1.3 English

These criteria must be met when choosing an oscillator for a design with GTY transceivers:

  • Provide AC coupling between the oscillator output pins and the dedicated GTY transceiver Quad clock input pins.
  • Ensure that the differential voltage swing of the reference clock is the range as specified in the Versal device data sheets. The nominal range is 250 mV–2000 mV and the nominal value is 1200 mV).
  • Meet or exceed the reference clock characteristics as specified in the Versal device data sheets.
  • Meet or exceed the reference clock characteristics as specified in the standard for which the GTY transceiver provides physical layer support.
  • Fulfill the oscillator vendor's requirement regarding power supply, board layout, and noise specification.
  • Provide a dedicated point-to-point connection between the oscillator and GTY transceiver Quad clock input pins.
  • Keep impedance discontinuities on the differential transmission lines to a minimum (impedance discontinuities generate jitter).