RX Fabric Clock Output Control

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

The RX clock divider control block has two main components: serial clock divider control and parallel clock divider and selector control. The clock divider and selector details are illustrated in the figure below.

Figure 1. RX Serial and Parallel Clock Divider

Notes related to the figure:

  1. CH*_RXOUTCLK is used as the source of the interconnect logic clock via BUFG_GT.
  2. Note that the RPLL and LCPLL from HSCLK0 can only be used by RX channel 0/1, and RPLL and LCPLL from HSCLK1 can only be used by RX channel 2/3.
  3. The selection of the /4, /5, /8, /10, /16, and /20 divider block, and the /1 and /2 divider block is made based on RX_DATA_WIDTH and RX_INT_DATA_WIDTH.
  4. For details about placement constraints and restrictions on clocking resources (such as BUFG_GT and BUFG_GT_SYNC), refer to the Versal Adaptive SoC Clocking Resources Architecture Manual (AM003).
  5. The clock output from IBUFDS_GTE5 should only be used after GTPOWERGOOD asserts High.