Driving the TX Interface

Versal Adaptive SoC GTY and GTYP Transceivers Architecture Manual (AM002)

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1.3 English

Depending on the TXUSRCLK frequency, there are different ways Versal architecture clock resources can be used to drive the parallel clock for the TX interface. Figure 1 shows that TXOUTCLK is from the PMA, and the TXOUTCLKCTL = 3'b010 to select the TXPHYCLK path as indicated in TX Fabric Clock Output Control.

  • Depending on the input reference clock frequency and the required line rate, a BUFG_GT with the appropriate TXOUTCLKCTL setting is required. The Versal Adaptive SoC Transceivers Wizard creates a sample design based on different design requirements for most cases.
  • When TXOUTCLK from one lane is used to drive multiple lanes (TXUSRCLK), the corresponding PLL for each lane must share the same reference clock.
  • In use models where the TX buffer is bypassed, there are additional restrictions on the clocking resources. Refer to TX Buffer Bypass for more information.