When and Where to Use a Reset - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

AMD devices have a dedicated global set/reset signal (GSR). This signal sets the initial value of all sequential cells in hardware at the end of device configuration.

If an initial state is not specified, sequential primitives are assigned a default value. In most cases, the default value is zero. Exceptions are the FDSE and FDPE primitives that default to a logic one. Every register will be at a known state at the end of configuration. Therefore, it is not necessary to code a global reset for the sole purpose of initializing a device on power up.

AMD highly recommends that you take special care in deciding when the design requires a reset, and when it does not. In many situations, resets might be required on the control path logic for proper operation. However, resets are generally less necessary on the data path logic. Limiting the use of resets:

  • Limits the overall fanout of the reset net.
  • Reduces the amount of interconnect necessary to route the reset.
  • Simplifies the timing of the reset paths.
  • Results in many cases in overall improvement in clock frequency, area, and power.

Functional simulation should easily identify whether a reset is needed or not.

For logic in which no reset is coded, there is much greater flexibility in selecting the device resources to map the logic.

The synthesis tool can then pick the best resource for that code to arrive at a potentially superior result by considering, for example:

  • Requested functionality
  • Clock period requirements
  • Available device resources
  • Power