Placement Analysis - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Use the timing summary report after placement to check the critical paths.

  • Paths with very large negative setup time slack might require that you check the constraints for completeness and correctness, or logic restructuring to achieve timing closure.
  • Paths with very large negative hold time slack are most likely due to incorrect constraints or bad clocking topologies and should be fixed before moving on to route design.
  • Paths with small negative hold time slack are likely to be fixed by the router. You can also run report_clock_utilization after place_design to view a report that breaks down clock resource and load counts by clock region.

For more information on placement, see this link in the Vivado Design Suite User Guide: Implementation (UG904).