Reset Coding Example: Multiplier with Synchronous Reset - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

To take advantage of the existing DSP primitive features, the following example shows a multiplier with synchronous reset.

Figure 1. Multiplier with Pipeline Registers (Synchronous Reset)

In this circuit, the DSP48 primitive is inferred with all pipeline registers packed within the DSP primitive (AREG/BREG=1, MREG=1, PREG=1).

The following figure shows the coding example for multiplier pipeline registers that use a synchronous reset.

Figure 2. Synchronous Reset Coding Example

This coding example has the following advantages:

  • Optimal resource usage
  • Better performance and lower power
  • Lower number of endpoints