Input Ports - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

You can use an input port as the primary clock root as shown in the following figure.

Figure 1. create_clock for Input Ports

Constraint example:

create_clock -name SysClk -period 10 -waveform {0 5} [get_ports sysclk]

In this example, the waveform is defined to have a 50% duty cycle. The -waveform argument is shown above to illustrate its usage and is only necessary to define a clock with a duty cycle other than 50%. For more information, see the create_clock Tcl command in the Vivado Design Suite Tcl Command Reference Guide (UG835). For a differential clock input buffer, the primary clock only needs to be defined on the P-side of the pair.