Baselining and Timing Constraints Validation Procedure - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-06-26
Version
2024.1 English

The following procedure helps track your progress towards timing closure and identify potential bottlenecks:

  1. Open the synthesized design.
  2. Run report_timing_summary -delay_type min_max, and record the information shown in the following table.
    Table 1. Timing Summary Report for Synthesized Design
      WNS TNS Num Failing Endpoints WHS THS Num Failing Endpoints
    Synth            
  3. Open the post-synthesis report_timing_summary text report and record the no_clock section of check_timing.

    Number of missing clock requirements in the design: ___________

  4. Run report_clock_networks to identify primary clock source pins/ports in the design. (Ignore QPLLOUTCLK and QPLLOUTREFCLK because they are pulse-width only checks.)

    Number of unconstrained clocks in the design: ___________

  5. Run report_clock_interaction -delay_type min_max and sort the results by WNS path requirement.

    Smallest WNS path requirement in the design: ___________

  6. Sort the results of report_clock_interaction by WHS to see if there are large hold violations (>500 ps) after synthesis.

    Largest negative WHS in the design: ___________

  7. Sort results of report_clock_interaction by Inter-Clock Constraints and list all the clock pairs that show up as unsafe.
  8. Upon opening the synthesized design, how many Critical Warnings exist?

    Number of synthesized design Critical Warnings: ___________

  9. What types of Critical Warnings exist?

    Record examples of each type.

  10. Run report_high_fanout_nets -timing -load_types -max_nets 25.

    Number of high fanout nets not driven by FF: ___________

    Number of loads on highest fanout net not driven by FF: ___________

    Do any high fanout nets have negative slack? If yes, WNS = ___________

  11. Implement the design. After each step, run report_timing_summary and record the information shown in the following table.
    Table 2. Timing Summary Report
      WNS TNS Num Failing Endpoints WHS THS Num Failing Endpoints
    Opt            
    Place            
    Physopt            
    Route            
  12. Run report_exceptions -ignored to identify if there are constraints that overlap in the design. Record the results.