Moving Past Synthesis - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Be sure that the netlist you obtained during synthesis is of good quality so that it does not create problems downstream. The following sections cover important items to check before proceeding with the rest of the implementation flow.