User-Defined Generated Clocks - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

When all the primary clocks have been defined, you can use the Clock Networks or Check Timing (no_clock) reports to identify the clock tree portions that do not have a timing clock and define the generated clocks accordingly.

It is sometimes difficult to understand the transformation performed by a cone of logic on the master clock. In this case, you must adopt the most conservative constraint. For example, the source pin is a sequential cell output. The master clock is at least divided by two, so the proper constraint should be, for example:

create_generated_clock -name clkDiv2 -divide_by 2 \
-source [get_pins fd/C] [get_pins fd/Q]

Finally, if the design contains latches, the latch gate pins also need to be reached by a timing clock and will be reported by Check Timing (no_clock) if the constraint is missing. You can follow the examples above to define these clocks.