Example of Upfront Hierarchical Planning for High Speed DSP Designs - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The following example is not applicable to all designs, but demonstrates what can be done with hierarchy. DSP designs generally allow latency to be added to the design. This allows registers to be added to them to implement a higher clock frequency design. In addition, registers can be used to increase placement flexibility. This is important because at high clock frequency, signals cannot traverse the die in one clock cycle. Adding registers can allow hard-to-reach areas to be used. The following figure shows how effective hierarchy planning results in faster timing closure.

Figure 1. Effective Hierarchy Planning Example

There are three levels of hierarchy in this part of the design:

  • DSP_i

    In the DSP_i algorithm block, both the inputs and outputs are registered. Because registers are plentiful in a device, it is preferable to use this method to improve the timing budget.

  • floorplanning_wrapper_i

    In floorplanning_wrapper_i, there is a CE signal. CE signals are typically heavily-loaded and can present a timing challenge. They should be included in a floorplan. By creating a floorplanning wrapper, this module can be manually floorplanned later if needed.

    In addition, KEEP_HIERARCHY has been added at the module level to ensure that hierarchy is preserved for floorplanning regardless of any other global synthesis options.

  • placement_flexibility_wrapper_i

    In placement_flexibility_wrapper_i, the DATA_IN, VALID_IN, DATA_OUT and VALID_OUT signals are registered. Because these signals are not intended to be part of the floorplan, they are outside floorplanning_wrapper_i. If they were in the floorplan, they would not be able to fulfill the requirement for placement flexibility.

    In addition, more registers can be added later as long as both DATA_IN + VALID_IN or DATA_OUT and VALID_OUT are treated as pairs. If more registers are added, the synthesis tool might infer shift register LUTs (SRLs), which will force all registers into one component and not help placement flexibility. To prevent this, SHREG_EXTRACT has been added at the module level and set to NO.