Designing with HBM Devices - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

AMD Virtex™ UltraScale+™ HBM devices incorporate 4 GB high-bandwidth memory (HBM) stacks adjacent to the device die. Using SSI technology, the device communicates to the HBM stacks through memory controllers that connect through the silicon interposer at the bottom of the device. Each Virtex UltraScale+ HBM device contains one or two 4 GB HBM stacks, resulting in up to 8 GB of HBM per device. The device includes 32 HBM AXI interfaces used to communicate with the HBM. The flexible addressing feature that is provided by a built-in switch allows for any of the 32 HBM AXI interface to access any memory address on either one or both of the HBM stacks. This flexible connection between the device and the HBM stacks is helpful for floorplanning and timing closure.

The following figure shows the Virtex UltraScale+ HBM vu37p device adjacent to a Virtex UltraScale+ vu13p device. In the vu37p device, the bottom two SLRs of the vu13p device are replaced by the HBM stacks (SLR0 in the vu13p device) and an SLR that contains the 32 HBM AXI interfaces (SLR1 in the vu13p device). The top two SLRs of the vu13p and vu37p device are identical.

Figure 1. Device View of the vu13p and vu37p

In the vu37p device, the SLR0 contains 4 PCIE4C sites, 2 ILKNE4 sites, and the 32 HBM AXI interfaces. The 4 PCIE4C sites in the Virtex UltraScale+ HBM SLR0 are unique because they allow for the Cache Coherent Interconnect for Accelerators (CCIX) protocol using PCIe Gen3 x 16 when VCCINT is at 0.72V.

Figure 2. SLR0 of a Virtex UltraScale+ HBM vu37p Device