Clock Domain Crossing - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The clock domain crossing (CDC) circuits in the design directly impact design reliability. You can design your own circuits, but the Vivado Design Suite must recognize the circuit and you must apply the ASYNC_REG attributes correctly. AMD provides XPMs to ensure correct circuit design, including:

  • Driving specific features in place_design that reduce mean time between failures (MTBF) on synchronization circuits.
  • Ensuring recognition by report_synchronizer_mtbf.
  • Avoiding report_cdc errors and warnings, which typically show up late in the design cycle when iterations are longer.
Tip: For CDC violations that can be safely ignored, you can use the waiver mechanism to waive the violations. For details, see this link in the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).

A CDC circuit is required when crossing between two asynchronous clocks or when attempting to relax timing between two synchronous clocks by adding false path constraints. When using XPMs, you can select a single-bit or a multi-bit bus to cross between the domains.