Super Long Line (SLL) Routes - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

Super Long Line (SLL) routes connect signals from one SLR to another inside the device.

Tip: To determine the number of available SLLs between SLRs, use SLR properties. For example:
get_property NUM_TOP_SLLS [get_slrs SLR0]
get_property NUM_BOT_SLLS [get_slrs SLR1]