Disable LUT Combining - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English
Note: This optimization technique is automatically applied by the report_qor_suggestions Tcl command.

LUT combining reduces logic utilization by combining LUT pairs with shared inputs into single dual-output LUTs that use both O5 and O6 outputs. However, LUT combining can potentially increase congestion because it tends to increase the input/output connectivity for the slices. If LUT combining is high in the congested area (> 40%), you can try using a synthesis strategy that eliminates LUT combining to help alleviate congestion. The Flow_AlternateRoutability synthesis strategy and directive instructs the synthesis tool to not generate any additional LUT combining.

Note: If you are using Synplify Pro for synthesis, you can use the Enable Advanced LUT Combining option in the Implementation Options under the Device tab. This option is on by default. If you are modifying the Synplify Pro project file (*prj), the following is specified: set_option -enable_prepacking 1.

You can use the following command to select cells with LUT combining enabled in your design:

select_objects [get_cells -hier -filter {SOFT_HLUTNM != "" || HLUTNM != ""}]

The following figure shows the horizontal congestion of a design with and without LUT combining. The cells with LUT combining are highlighted in purple.

Figure 1. Effect of LUT Combining on Horizontal Congestion

To disable LUT combining on a module that overlaps with areas of higher congestion, use the following Tcl command:

reset_property SOFT_HLUTNM [get_cells -hierarchical -filter {NAME =~ <module name> && SOFT_HLUTNM != ""}]