SelectIO Clocking - 2024.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2024-05-30
Version
2024.1 English

The UltraScale device SelectIO primitives have maximum skew requirements between clock pins. Using the optimal clocking topology for the SelectIO primitives prevents maximum skew violations, improves interface timing between the UltraScale device and the fabric logic, and uses fewer clocking resources.